Semiconductor lasers are used in various fields, and intensive studies are being made to develop drive circuits for driving the semiconductor lasers (see Japanese Unexamined Patent Publication No. 2001-244556, for example). FIG. 1 illustrates a typical example structure of a LD drive circuit for direct modulation that performs modulation by switching on and off the current for controlling the light emission from a semiconductor laser. The LD drive circuit for direct modulation includes differential amplifiers arranged in stages, as shown in FIG. 1, and has a duty variable function and an output shutdown function for shutting down outputs from a laser diode.
A first amplifier 2 shown in FIG. 1 is a duty control amplifier, and a second amplifier 3 functions as a buffer amplifier. Amplifiers 5 and 6 in the stages after an AND gate 4 function as amplifiers for amplification.
FIG. 2 illustrates the circuit structure of the AND gate 4. The AND gate 4 includes: a differential FET pair 7 and 8 that capture a main signal for switching on and off a semiconductor laser; a differential FET pair 10 and 11 for data clamping; and a FET 12 that is placed below the shared source of the differential FET pair 10 and 11, and functions as a current source. The differential FET pair 10 and 11 function as a clamping circuit 9.
The first amplifier 2 superimposes a duty control signal that controls the duty ratio of the main signal to the main signal for controlling the switching on and off of the semiconductor laser. To change the duty ratio of the main signal, the output signal of the first amplifier 2 has the waveforms shown in FIG. 3B. FIG. 3A shows the main signal to be input to the first amplifier 2. FIG. 3B shows the output signal of the first amplifier 2. As shown in FIG. 3B, the main signal after the duty ratio control is an unstable signal that has different voltage levels between the normal side and the inverted side.
In recent years, +3.3V power sources are widely used as operation power sources, and the margin between signals is becoming smaller as the voltage to be applied is becoming lower. Under such circumstances, when signals having different voltage levels are input directly to the AND gate 4 shown in FIG. 2, the AND gate 4 might malfunction and fail to operate properly, and the outputs of the clamping circuit 9 might not be maintained at uniform levels.
To counter this problem, the second amplifier 3 as a buffer is interposed between the first amplifier 2 and the AND gate 4 in the conventional LD drive circuit. With this arrangement, a main signal is input to the AND gate 4, after the level of the main signal having an adjusted duty ratio is adjusted.
As described above, the conventional LD drive circuit needs to have a buffer amplifier for signal level adjustment (the second amplifier 3), and has the problem of larger power consumption.
In a case where the duty ratio of a main signal is adjusted by superimposing the main signal with a duty control signal, the duty variable characteristics are varied with the amplitude of the main signal. For example, if the amplitude of the main signal is large, the variation in the duty ratio of the main signal is small, even after the duty ratio is adjusted by superimposing the main signal with a duty control signal. If the amplitude of the main signal is small, the duty ratio of the main signal is greatly varied after the duty ratio is adjusted by superimposing the main signal with a duty control signal.
In a case where the number of amplifier stages is reduced by giving a gain to the buffer amplifier for signal level adjustment (or the buffer amplifier also serves as a driver amplifier), the clamping circuit 9 of the AND gate 4 needs to thoroughly clamp the signal amplified by the second amplifier 3. As a result, the transistor becomes larger in size.